1. Field of the Invention
The present invention relates to a manufacturing method of a non-volatile semiconductor memory device and more particularly to a non-volatile semiconductor memory device manufacturing method for forming a non-volatile memory transistor of a two-level gate electrode structure made up of a floating gate electrode and a control gate electrode, and a MOS transistor of a single gate electrode structure for a peripheral circuit, on a single semiconductor substrate.
2. Description of the Related Art
In a non-volatile memory transistor of a two-level gate electrode structure made up of a floating gate electrode and a control gate electrode, one important point for realizing excellent performance is to provide a large capacitive coupling between the control gate and the floating gate.
As an interlayer insulating film between the control gate and the floating gate, a thermal oxide film of polysilicon forming the floating gate electrode has been widely used. However, in order to increase the capacitive coupling without sacrificing the area of a memory cell, it becomes necessary to thin the thermal oxide film. But, the polysilicon oxide film causes a current to more readily flow therethrough as compared with the thermal oxide film of a single crystalline silicon and has a low breakdown voltage, and therefore, it is difficult to form a thin polysilicon oxide film.
On the other hand, if an interlayer insulating film can be made of a material having a permittivity higher than that of an oxide film, it is possible to increase the capacitive coupling without forming a thin oxide film. Therefore, in JP-A-60-145666 (laid open on Aug. 1, 1985) or JP-A-61-229368 (laid open on Oct. 13, 1986), there is disclosed a non-volatile memory device in which an interlayer insulating film is formed by a two layer film made up of a thin silicon oxide film and a silicon nitride film of a high permittivity on the basis of the above conception. Further, in JP-B-2-2310 (published on Jan. 17, 1990 and corresponding to JP-A-60-167377 laid open on Aug. 30, 1985) and JP-B-2-2311 (published on Jan. 17, 1990 and corresponding to JP-A-60-167378 laid open on Aug. 30, 1985), there is disclosed a non-volatile memory device and a method of manufacturing the same in which thin silicon oxide films are provided on the upper and lower sides of a silicon nitride film to form an interlayer insulating film.
A method employing a high permittivity material for an interlayer insulating film in such a manner is also advantageous in the respect of a low temperature manufacturing process. In the case where the thermal oxide film of the polysilicon is used for the interlayer insulating film, the oxidation at high temperature from 1000.degree. C. to 1150.degree. C. or so is necessary to limit a leakage current to a tolerance of a data retention characteristic. On the other hand, in the above publications, there is shown that if a silicon nitride film by the chemical vapor deposition method (CVD method) is used, the temperature of the process including the formation of a thin film silicon oxide film can be lowered to a range of 800.degree. C. to 900.degree. C. or so.
On the other hand, in JP-A-61-421717 (laid open on Feb. 28, 1986) and JP-A-62-150781 (laid open on Jul. 4, 1987), there is disclosed a manufacturing method of forming a non-volatile memory transistor employing a polysilicon oxide film as an interlayer insulating film and a MOS transistor of a single gate electrode structure for a peripheral circuit on a single semiconductor substrate.
More specifically, in JP-A-61-42171, there is disclosed a manufacturing method in which two conductive layers (e.g., polysilicon films) are used, a two-level type gate electrode of a memory transistor is formed by first and second level conductive layers and a single gate electrode of a MOS transistor for a peripheral circuit is formed by the second level conductive layer.
Further, in JP-A-62-150781, there is disclosed a manufacturing method in which three conductive layers are used, a two-level type gate electrode of a memory transistor is formed by first and second level conductive layers, and a single gate electrode of a MOS transistor for a peripheral circuit is formed by the second and third level conductive layers.
In order to operate a non-volatile memory transistor of a two-level gate electrode structure as a memory cell of a non-volatile memory device, it is necessary to form the non-volatile memory transistor and the MOS transistor used with a peripheral circuit for driving the former on a single semiconductor substrate.
As already described, with respect to the formation of the interlayer insulating film of the non-volatile memory device by the polysilicon oxide film, the manufacturing method suitable therefor is clarified as a public known art. However, if it is intended to utilize a high permittivity material, such as a silicon nitride film as described in the prior art, in at least part of the interlayer insulating film, the following problems will arise in the combination of the prior art.
That is, when a high permittivity material such as a silicon nitride film is used for the interlayer insulating film, it is natural that the interlayer insulating film and the gate oxide film of the MOS transistor for a peripheral circuit should be formed in different two processes. However, the two processes exert a bad influence on each other, and therefore, it is difficult to maintain the reliability of the interlayer insulating film and the gate oxide film.
More specifically, in the area of the substrate in which the MOS transistor for a peripheral circuit is to be formed, the gate oxidation is carried out after removing the high permittivity film provided as the interlayer insulating film of the memory transistor. However, the contamination or damage of a portion of the substrate which is exposed during the removal of the high permittivity film loweres the reliability of the gate oxide film.
In other words, when the silicon nitride film in the memory transistor area is covered with a photoresist and the silicon nitride film in the peripheral circuit MOS transistor portion is removed by the dry etching technique, the etching rate ratio between the silicon nitride film and the silicon oxide film cannot be sufficiently taken, and therefore, the silicon oxide film under the silicon nitride film in the peripheral circuit MOS transistor portion is also subjected to the dry etching process. As a result, the surface of the silicon substrate under the etched silicon oxide film is damaged, or heavy metal and the like from the dry etching system are introduced into the surface of the silicon substrate thereunder to contaminate that surface.
Moreover, since the interlayer insulating film in the memory transistor area is also covered with the photoresist film during the process of removing the silicon nitride film, or is subjected to the pre-washing process prior to the formation of the gate oxide film in the peripheral circuit area, a leakage current is increased in a low electric field and it is difficult to maintain a sufficient breakdown voltage.
On the other hand, in JP-A-2-84776 (laid open on Mar. 26, 1990), for the purpose of overcoming the plasma damage due to the dry etching for the gate insulating film in the peripheral circuit MOS transistor portion and the interlayer insulating film of a two-level gate electrode structure in the memory transistor portion, there is disclosed a manufacturing method of a non-volatile semiconductor memory device as will hereinbelow be described.
According to this method, after a silicon nitride film is further formed on the interlayer insulating films of three layers made up of a silicon oxide film, a silicon nitride film and a silicon oxide film each serving as an interlayer insulating film for a two-level gate electrode structure in a memory transistor portion of the non-volatile semiconductor memory device, four layers made up of the silicon nitride film, the silicon oxide film, the silicon nitride film and the silicon oxide film in the peripheral circuit MOS transistor portion are etched in this order with a photoresist pattern being partially left in the memory cell portion, and the photoresist pattern is removed by the asher treatment with some silicon oxide film of the lowest layer being left on the substrate, whereby the three layers of the silicon oxide film, the silicon nitride film and the silicon oxide film are covered with the uppermost silicon nitride film and the surface of the silicon substrate in the peripheral circuit MOS transistor portion is covered with the silicon oxide film of the lowest layer to prevent the influence of the plasma asher.